1. Field of the Invention
The present invention relates to a Bi-CMOS circuit, and particularly, to a CMOS-TTL high-speed conversion output buffer.
2. Description of the Related Art
As the demand for an improved operation speed and a lowering of the power consumption of computer systems increases, greater integration, speed, and lower power consumption are required from LSIs. In an effort to meet these requirements, Bi-CMOS LSIs are now under development.
FIG. 3 shows an output buffer of a conventional Bi-CMOS LSI, the output of which is realized with TTL circuitry. In the figure, numerals 10 and 20 denote first and second CMOS inverters, 30 denotes a totem-pole type bipolar output stage, MP represents a p-channel MOS transistor, MN represents an n-channel MOS transistor, Q1, Q2 and Q3 denote bipolar transistors, SD.sub.1 and SD.sub.2 denotes Schottky barrier diodes (SBDs), and R.sub.1 and R.sub.2 denote resistors.
When an input IN of this circuit is high (H), MN1 turns and the MP1 turns OFF to thus make an output node "a" low (L). This turns the MP2 ON and the MN2 OFF, to thereby make an output node "b" H, which turns ON Q3, turns OFF Q1 and Q2, and turns ON MP3, to thereby make an output OUT L.
When the input IN is L, the MP1 is turned ON and the MN1 is turned OFF, to make the node "a" H. This turns the MP2 OFF and turns the MN2 ON, thereby setting the node "b" L, whereby Q3 is turned OFF, Q1 and Q2 are turned ON, and the MP3 is turned OFF, thereby making the output OUT H. The transistor MP3 is used to discharge a base of the transistor Q2.
As shown in the figure, the conventional Bi-CMOS TTL-type output buffer comprises two CMOS inverter stages and a bipolar output stage; the CMOS inverter stages are arranged in series, to generate signals for driving transistors of the bipolar output stage.
Namely, the output stage 30 comprises the npn transistors Q1 and Q2 having a Darlington connection for pulling up the output end OUT, and the npn transistor Q3 for pulling down the output end OUT. The transistor Q1 on the pull-up side is driven by an output of the node "a", i.e., an output of the first CMOS inverter stage, and the transistor Q3 on the pull-down side is driven by an output of the node "b", i.e., an output of the second CMOS inverter stage.
In this arrangement, a change from L to H (pulling up) at the output OUT is slightly delayed with respect to the input IN, and a change from H to L (pulling down) at the output OUT is significantly delayed with respect to the input IN. This unbalanced state of a quick rise and slow fall may cause a fluctuation of a duty ratio of an output waveform, and thus this problem an unbalanced state must be taken into account when designing the circuit, and gates added for adjusting the duty ratio.